Digital Gauges: Frequently Asked Questions
Question number FAQ-0065
DG-4240/4280 Terminal Block Input Signal Timing Chart
This section explains the timing chart of signals input from the terminal block.
Input can be via voltage-free relay contacts or open collector signals. When connecting to a sequencer, input via terminal block is recommended over input via BCD connector.
Signals input via BCD connectors respond faster than those input via terminal blocks. However, this also means that extra caution is needed regarding noise. Please refer to the instruction manual for details.
■ Example of terminal block input circuit and sequencer connection
■ Terminal block HOLD, RESET, GATE input circuits
<1> Timing chart for hold input, BUSY input, and print command output
When importing data into a sequencer or similar device, apply a hold signal to ensure the BCD signal is stable before importing. If you import without applying a hold signal, be aware that data may not be read correctly if the data is acquired at a time when the BCD data changes.
T1
The maximum time from when the hold signal is input until the displayed value and BCD output data are held is 4ms.
T2
This is the time from when the displayed value and BCD output data are held until the print command signal is output, and it is a maximum of 10 μs.
T3
The pulse width of the print command signal is 100 to 150 μs.
T4
The time between the release of the hold signal and the release of the hold state is a maximum of 150ms.
T5
The minimum time between releasing the hold signal and re-entering it is 160ms. If the hold signal is entered at a shorter interval than this, the print command signal may not be output.
<2> Reset signal timing chart
The pulse width of the reset input signal must be at least 4ms. The time from the input of the reset signal to the reset state must be a maximum of 4ms. The time from the release of the reset signal to the end of the reset state must be a maximum of 150ms.
<3> Timing chart of comparator gate input signal
This is used to forcibly turn off the pass/fail judgment output. The pulse width of the comparator gate signal must be at least 4ms. The time from inputting the comparator gate signal until the function activates is a maximum of 4ms. The time from releasing the comparator gate signal until the function is deactivated is a maximum of 150ms.
Last updated: 2000-12-08